The present invention relates to a semiconductor integrated circuit and a designing technique thereof and particularly relates to an effective technique for suppressing optical proximity effect.
In a semiconductor integrated circuit, main factors of dispersion of propagation delay time of signals are dispersion of power supply voltage in operation, dispersion of temperature, dispersion in the manufacturing process, and the like. The semiconductor integrated circuits must be designed so that the operation thereof is guaranteed even when all the above factors of dispersion become the worst. Particularly, gate length of a transistor plays a significant role for defining the operation of the transistor, and dispersion of gate length occupies large in the factors of dispersion in the process. Further, in recent years, the gate length becomes smaller and smaller in association with development of transistor miniaturization to display a tendency for increasing a ratio of influence of dispersion of gate length to the dispersion in the manufacturing process. For this reason, the dispersion of propagation delay time increases, which in turn requires a large design margin to make it difficult to provide a high performance semiconductor integrated circuit.
Furthermore, in the process of manufacturing a semiconductor integrated circuit, in general, a photolithography step including resist application, exposure, and development, an etching step for element patterning using a resist mask, and a resist removing step are repeated to form a integrated circuit on a semiconductor substrate. In forming a gate of a transistor, the photolithography step, the etching step, and the resist removing step are performed. In exposure in the photolithography step, when the pattern dimension is smaller than the wavelength of exposure light, optical proximity effect by an influence of diffracted light makes error between a layout dimension at design and an actual pattern dimension in the semiconductor substrate large.
Under the circumstances, it is essential to perform correction for suppressing dimensional error of the pattern which is caused by the optical proximity effect at rendering or exposing of a pattern such as a wiring pattern in the semiconductor integrated circuit. OPC (Optical Proximity effect Correction) is known as a technique for correcting the optical proximity effect. OPC is a technique in which an amount of variation in gate length caused by the optical proximity effect is predicted from the distance between a gate and another adjacent gate pattern and a mask value of a photoresist mask for forming the gate is corrected so as to cancel the amount of variation to bring the finished value of the gate length after exposure consistent.
In conventional layout techniques, since gate patterns are not standardized, and the gate length and the gate intervals are different part from part in an entire chip, correction by OPC is necessary. However, the gate mask correction through OPC invites delay in TAT (Turn Around Time) and an increase in processing amount.
In order to avoid the foregoing, a technique is proposed in which the gate length and the gate intervals are equalized to respective single values for layout. In this proposal, by circuit design with the gate length of a single value or by inserting a dummy gate playing no role as an actual element for equalizing the gate intervals, the finished value of the gate length becomes consistent surely even without performing gate mask correction by OPT. However, this lowers outstandingly the flexibility of design, inviting degradation of circuit characteristics and an increase in chip area. Under the circumstances, means is desired to be established which can suppresses dispersion of gate length by the optical proximity effect even with arbitrary gate length and arbitrary gate intervals.
A related technique is disclosed in Japanese Patent Application Laid Open Publication No. 10-32253A, for example.
As described above, the gate length is shortened in association with development of transistor miniaturization, and the influence of the optical proximity effect by diffracted light becomes significant in gate exposure. The OPC technique remarkably improves dependency of the finished dimension of the gate length, which varies due to the influence of the optical proximity effect, on a neighboring pattern. However, the dependency of the finished dimension of the gate length on the neighboring pattern cannot be correct thoroughly in all standard cells. Further, if the gate length and/or gate intervals are equalized for insisting on improving correction accuracy through the OPC technique, the flexibility of design would be too limited.